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HBM vs Advanced DRAM: A Simple Explainer for Non-Engineers (Part 1)
Your PC's memory and an AI superchip's memory look nothing alike — even though they are made of the same silicon. One is a removable stick sitting inches away from your processor. The other is a skyscraper of 12 memory dies stacked directly on top of your GPU, connected by 10,000 microscopic wires.
In this 12,000-word series, we will unpack why that difference exists, why it is driving a global RAM shortage in 2026, and why HBM — High Bandwidth Memory — is now more important than the GPU itself.
Why HBM vs Advanced DRAM Matters Right Now (2026)
If you tried to build a PC in late 2025 or 2026, you noticed it: DDR5 kits that were $89 are now $249. Gamers blame Nvidia. PC builders blame inflation. The real culprit is happening inside the same factories that make your RAM.
Three companies — Samsung (~50%), SK Hynix (~40%), and Micron (~10%) — make ~90% of the world's DRAM. The same three make 100% of the world's HBM. Both HBM and DDR5 are made on the same wafer lines, in the same clean rooms.
When Nvidia offers to pay 5x more per bit for HBM3E than a consumer pays for DDR5, the economic decision is obvious: shift wafer capacity to HBM. Consumer supply drops 10% overnight, prices spike 300-700%. That's the core of the class-action lawsuit filed in 2026 against the three DRAM makers — and the reason understanding HBM is no longer optional.
Full Series Table of Contents (6-10 Parts)
- Part 1: Foundations - What DRAM Really Is (You Are Here) - SRAM vs DRAM, DDR evolution, why DDR5 is "Advanced DRAM"
- Part 2: Advanced DRAM Deep Dive - DDR5, LPDDR5X, CAMM2, GDDR6/6X/7 - speeds, PMIC, on-die ECC, channels
- Part 3: What Is HBM? The Skyscraper Architecture - TSVs, interposer, stacking, base die, why proximity matters
- Part 4: Head-to-Head - HBM vs DDR vs GDDR - Bandwidth, latency, capacity, power, cost, repairability table
- Part 5: Why AI Broke Memory - The Memory Wall - Training vs inference, KV cache, why GPUs sit idle
- Part 6: The Business War - SK Hynix vs Samsung vs Micron - Yields, CoWoS packaging, Nvidia supply chain
- Part 7: HBM3E, HBM4 & Beyond - 2048 I/O pins, 4nm base die, 40% efficiency, what's next
- Part 8: Practical Impact & Buyer's Guide - Should you wait to buy RAM? What CXMT and CXL mean
- FAQ, Glossary, and Resource List
Foundational Concept 1: SRAM vs DRAM - The Two Types of Memory You Actually Use
Your computer uses two completely different memory technologies without you ever seeing it:
SRAM (Static RAM) is made of flip-flop circuits. It never needs to be refreshed, it's blisteringly fast, but it's huge and expensive — like a sports car parking lot where each parking spot costs $10,000. That's why it's used inside your CPU as L1/L2/L3 cache, only a few megabytes.
DRAM (Dynamic RAM) is made of a capacitor + transistor — one tiny bucket that leaks. It must be refreshed thousands of times per second, but it's 10x denser and cheaper. That's your main memory — your 16GB, 32GB sticks, your phone's memory, and yes, your graphics memory.
Important: DDR5, GDDR6, LPDDR5X, and HBM are ALL types of DRAM. Same bucket technology, just packaged and wired differently to trade latency for bandwidth.
Watch: TechQuickie explains why your PC doesn't use HBM — sponsored by Micron engineers.
Foundational Concept 2: What Makes DRAM "Advanced"? DDR to GDDR
If DDR3 was a two-lane road, Advanced DRAM is an 8-lane highway with better traffic lights.
DDR5 - The Desktop Standard
- Double Data Rate: Transfers on both rise and fall of clock — 2x data per tick.
- Two 32-bit sub-channels: DDR5 splits its 64-bit bus into two independent 32-bit channels — better for many small requests.
- On-die ECC + PMIC: DDR5 moves power management onto the stick itself, and adds error correction inside the chip. More reliable at higher speeds.
- Typical bandwidth: ~38-51 GB/s per DIMM at 4800-6400 MT/s.
GDDR6 / GDDR6X / GDDR7 - Graphics DRAM
GDDR is still DRAM, but soldered directly onto your graphics card PCB, inches from the GPU, with a much wider bus (256-bit to 384-bit) made of many chips working in parallel. GDDR6X uses PAM4 signaling — 4 voltage levels instead of 2 — to cram more bits per tick, at the cost of power and heat.
Result: An RTX 4090 with 24GB GDDR6X hits ~1 TB/s, but at 50W+ just for memory.
LPDDR5X - The Laptop/Phone Version
Low Power DDR — same tech, but voltage is lower and it sleeps aggressively. Soldered, not removable, to save space. Your phone and MacBook use it.
| Feature | DDR5 (System) | GDDR6X (Gaming GPU) | HBM3E (AI Accelerator) |
|---|---|---|---|
| Location | Motherboard slot, inches away | Soldered on PCB, inches away | On interposer, micrometers away |
| Bus Width | 64-bit (2x32) | 384-bit (12 chips x 32-bit) | 1024-bit per stack |
| Bandwidth per module | ~51 GB/s | ~1008 GB/s (total card) | ~1220 GB/s per stack |
| Power Efficiency | Moderate | Low (hot) | High - 30-40% less pJ/bit |
| Capacity | 16-128GB per DIMM | 8-24GB per card | 24-36GB per stack, 141GB per GPU (H200) |
| Removable? | Yes | No - requires desoldering | No - part of GPU package |
| Cost | $ | $$ | $$$$$ (5x DDR5 per bit) |
Why HBM Looks Like a Skyscraper
Standard DRAM lays chips flat on a board like houses in a suburb. Each house has a long driveway to the CPU. HBM stacks 8-12 DRAM dies vertically — like a 12-story apartment — and drills an elevator shaft (Through-Silicon Vias or TSVs) straight through all floors. The entire building sits on a shared basement (logic base die + silicon interposer) that is wired directly to the GPU.
Analogy for non-engineers: If DDR5 is 64 delivery trucks on a long highway, HBM is 1024 conveyor belts inside the same factory. Shorter distance, more belts, more boxes per second.
Why It Matters: Inference is memory-bound, not compute-bound. Double bandwidth = double tokens per second.
Who Benefits: SK Hynix, who bet early on HBM and now supplies ~70% of Nvidia HBM3E.
Risk: Same fabs make DDR5 and HBM. More HBM = less DDR5 = higher PC RAM prices.
FAQ - Part 1
Is HBM a completely new type of memory?
No. HBM is still DRAM — same capacitor bucket — just repackaged with 3D stacking, TSVs, and a wide 1024-bit interface on a silicon interposer to trade capacity and cost for extreme bandwidth.
Why doesn't my gaming PC use HBM?
Cost, capacity, and repairability. HBM costs ~5x per bit vs DDR5, cannot be upgraded, and requires advanced packaging (TSMC CoWoS) that is expensive. GDDR6 is good enough for gaming rasterization. AI needs HBM because it's memory-bound.
DDR5 vs GDDR6 vs HBM — which is fastest?
Per pin, GDDR7 is fastest (~32 Gbps/pin). Per stack/card, HBM3E is fastest (~1.2 TB/s per stack, ~4.8 TB/s per H200). Per DIMM, DDR5 is slowest (~50 GB/s) but has highest capacity and lowest cost.
In Part 2, we will dissect Advanced DRAM in detail — how DDR5's dual 32-bit channels, on-die ECC, and PMIC actually work, why GDDR6X uses PAM4 and runs hot, and why LPDDR5X and CAMM2 might kill the classic RAM stick.
[Part 1 Complete. Say "Go" or "Proceed" to generate Part 2.]
Part 2 of HBM vs Advanced DRAM: A Simple Explainer for Non-Engineers | Missed Part 1? It covered SRAM vs DRAM fundamentals and why 2026 RAM prices exploded.
Recap: What We Learned in Part 1
In Part 1 we established that all modern memory — DDR5 in your desktop, LPDDR5X in your phone, GDDR6X in your GPU, and HBM3E in an Nvidia H200 — is still DRAM: one capacitor that leaks and must be refreshed. The difference is packaging. DDR5 is a removable stick 6 inches from the CPU with a 64-bit bus. HBM is a 12-story skyscraper of dies stacked with Through-Silicon Vias (TSVs) sitting micrometers from the GPU with a 1024-bit bus. Same silicon, radically different highway to the processor.
DDR5 Under the Hood: Why It's Called "Advanced DRAM"
DDR4 vs DDR5 is not just "faster." JEDEC redesigned the core architecture because DDR4 hit a physics wall at ~3200 MT/s. Here is what actually changed for non-engineers:
1. Two Independent 32-bit Channels Instead of One 64-bit
DDR4 has one 64-bit channel per DIMM. If the CPU wants 32 bytes from one location and 32 bytes from another far away, it has to wait. DDR5 splits each DIMM into two independent 32-bit sub-channels. Think of a grocery store that had one checkout lane with a huge cart, now has two smaller express lanes — better for many small, random requests, which is exactly what modern CPUs do. Effective access efficiency goes up 10-15% even at same frequency.
2. Burst Length Doubled to 16, Banks Quadrupled
DDR5 increased Burst Length from 8 to 16 — each read command delivers 16 chunks instead of 8. To feed that, bank groups went from 4 to 8, total banks from 16 to 32. More banks = more places the memory can have data ready while other banks are recharging. Like having 32 microwaves instead of 16 in a cafeteria. Throughput goes up, but latency (the time to first bite) stays similar, around 70-80ns.
3. On-Die ECC Is NOT Real ECC
This confuses everyone. DDR5 includes on-die ECC inside each chip that corrects bit errors inside the chip before sending data out. Why? Because at 6000+ MT/s and tiny 10nm cells, bits flip inside the chip itself. This is NOT the side-band ECC that servers use to correct errors on the bus between chip and CPU. Consumer DDR5 is still not ECC-protected on the bus — if a cosmic ray flips a bit during transit, your system won't know. True ECC DDR5 (for workstations) adds an extra chip per DIMM, just like DDR4 ECC.
4. PMIC Moves Power to the Stick
DDR4 relied on the motherboard to regulate voltage (~1.2V). DDR5 moves a Power Management IC (PMIC) onto the DIMM itself, regulating down to 1.1V with much tighter tolerances. This allows higher speeds (6400 MT/s+) and better overclocking, but also makes DDR5 DIMMs hotter and $3-5 more expensive to build. Early DDR5 PMIC shortages in 2022-2023 were a major reason for price spikes — a preview of 2026.
LPDDR5X and the Death of the RAM Stick: CAMM2
LPDDR5X is what your phone, iPad, and new MacBook Air use. Same DDR core, but optimized for battery:
- Lower voltage: 0.5V-1.05V vs DDR5's 1.1V, with aggressive sleep states
- WCK clocking: A separate fast clock for data only, saving power when idle
- Soldered down: Not socketed — soldered directly to motherboard to reduce trace length and power. You cannot upgrade it.
LPDDR5X hits 8533 MT/s today at 6.4 Gbps per pin, with bandwidth around 68 GB/s per 64-bit package — beating DDR5 DIMMs in a package the size of a postage stamp.
CAMM2 - JEDEC's Replacement for SO-DIMM
In 2024, JEDEC ratified CAMM2 (Compression Attached Memory Module) to fix LPDDR's upgrade problem. Instead of soldering LPDDR chips, you mount them on a thin module that presses against the motherboard with a compression connector — no pins, no tall DIMM slot. Dell and Lenovo already ship CAMM2 laptops in 2026.
Why it matters: CAMM2 allows 128GB of LPDDR5X in a laptop thinner than 12mm, at 2x the bandwidth of SO-DIMM DDR5, at 40% less power. It is the future of laptop Advanced DRAM — and it looks like a flat circuit board, not a stick. DDR5 SO-DIMM will be legacy by 2027.
Quick history: DDR1 (2000) to DDR5 evolution - voltages, pins, bandwidth.
GDDR: The Graphics Memory That Powers Gaming
GDDR is where Advanced DRAM gets exotic. Same DRAM core, but redesigned for GPUs that need massive parallel bandwidth and can tolerate higher latency.
GDDR6 - The Workhorse (2018-Today)
16 Gbps per pin, 32-bit per chip, 8-12 chips in parallel to make a 256-384-bit bus. Total ~1 TB/s on RTX 4090. Uses NRZ (2 voltage levels) like DDR. Relatively cool and efficient.
GDDR6X - Nvidia's PAM4 Gamble (2020-2024)
Micron and Nvidia introduced PAM4 signaling — 4 voltage levels instead of 2 — encoding 2 bits per signal instead of 1. That pushed RTX 3090/4090 to 19-21 Gbps per pin and 1 TB/s+ bandwidth. Tradeoff: PAM4 is noisy, needs more power, runs 10-15C hotter, requires error correction. That's why RTX 4090 GDDR6X modules hit 95C under load. It's fast but expensive to cool.
GDDR7 - The Fix: PAM3 (2024-2026)
New RTX 50-series uses GDDR7. Instead of PAM4, it uses PAM3 — 3 levels, 1.5 bits per cycle. Slightly less dense than PAM4, but far more stable, lower power, and hits 32 Gbps per pin. Samsung's GDDR7 announcement claims 1.79 TB/s on RTX 5090 512-bit bus, at 20% lower power than GDDR6X. This is the last stop before HBM trickles down to gaming.
| Spec | DDR5 DIMM | LPDDR5X (soldered) | GDDR6X | GDDR7 (2026) |
|---|---|---|---|---|
| Speed per pin | 6.4 Gbps | 8.5 Gbps | 21 Gbps PAM4 | 32 Gbps PAM3 |
| Bus Width | 64-bit (2x32) | 64-bit | 384-bit (12 chips) | 512-bit |
| Total BW | 51 GB/s | 68 GB/s | 1008 GB/s | 1792 GB/s |
| Power per bit | ~4.5 pJ/bit | ~2.5 pJ/bit | ~7 pJ/bit | ~5.5 pJ/bit |
| Latency | ~75ns | ~90ns | ~120ns | ~110ns |
| Upgradeable? | Yes (for now) | No / CAMM2 yes | No | No |
Why This Advanced DRAM Still Hits a Wall
Even with GDDR7 at 1.79 TB/s, Nvidia's Blackwell B200 uses HBM3E — eight stacks delivering 8 TB/s total. Why? Two reasons:
1. Power: GDDR7 at 1.79 TB/s burns ~80W just for memory. 8 HBM3E stacks at 8 TB/s burn ~120W — 4.5x more bandwidth for 1.5x power. In a data center where electricity is 40% of TCO, that matters.
2. Space: 12 GDDR7 chips take ~6000 mm² of PCB. 8 HBM stacks take ~1200 mm² on interposer, right next to GPU. No long traces = no signal loss.
This is why Advanced DRAM — no matter how advanced — cannot catch HBM for AI. It's optimized for cost and capacity (DDR5) or raw speed at distance (GDDR). HBM is optimized for bandwidth-per-watt at near-zero distance.
Is DDR5 backward compatible with DDR4?
No. Different slot, different voltage (1.1V vs 1.2V), different PMIC, different pin count (288 vs 288 but keyed differently). You need a DDR5 motherboard and CPU with DDR5 memory controller (Intel 12th Gen+ or AMD AM5).
Is GDDR7 worth waiting for in gaming?
For 4K 144Hz, yes — 1.5-1.8 TB/s vs 1 TB/s is 30-40% more texture bandwidth. But price will be high in 2026. GDDR6X cards like RTX 4080 are still excellent value.
Will CAMM2 replace my desktop DDR5?
Not immediately. CAMM2 is for laptops first. JEDEC is developing CAMM2 for desktop in 2027, but it will take years to replace DIMMs. Your DDR5 DIMMs are safe until at least 2028.
Now that you understand how Advanced DRAM squeezes more bandwidth from flat, far-away chips, you can appreciate why engineers decided to stack memory like a skyscraper instead. In Part 3, we teardown HBM itself — the TSV elevator shafts, the silicon interposer basement, the logic base die, and why 1024 wires beat 64 wires every time.
[Part 2 Complete. Say "Go" or "Proceed" to generate Part 3.]
Part 3 of HBM vs Advanced DRAM | Part 2 covered DDR5, LPDDR5X, CAMM2, GDDR6/6X/7 deep dive.
What Is HBM? Why Engineers Built a Skyscraper for Memory
In 2015, AMD did something weird. Instead of putting faster GDDR chips around its Fiji GPU, it stacked memory on top of itself and placed it right next to the GPU on a piece of silicon. Reviewers called it exotic. Nvidia called it the future. That was HBM1 — High Bandwidth Memory.
Today, every AI accelerator — Nvidia H100/H200, B100/B200, AMD MI300, Google TPU v5p, Intel Gaudi 3 — uses HBM. Not because it's trendy. Because flat memory ran out of physics.
The Core Problem: Wires Don't Scale
DDR5 has 64 wires per DIMM. To get more bandwidth, you can make those wires faster (DDR5-6400) or add more DIMMs. But faster wires burn more power and create interference, and more DIMMs mean longer traces on the motherboard — signal degrades. GDDR6 solved this by adding 384 wires (12 chips x 32-bit), but now you need a huge PCB and 60W just for memory.
HBM solves it differently: go vertical.
The 4 Pieces That Make HBM Work
1. The DRAM Dies - The Apartments
A single HBM stack is 8 to 12 DRAM dies stacked directly on top of each other, each thinned to ~30 microns — thinner than human hair. Each die is a standard DRAM die (same core as DDR5) but with two extra features: TSV holes drilled through it, and a 128-bit slice of the 1024-bit bus.
HBM3E stacks 12 dies for 24GB (12 x 2GB x 8-high) or 36GB (12 x 3GB with 12-high). HBM4 will stack 16-high for 48GB per stack using hybrid bonding — no more micro-bumps, just copper-to-copper direct bonding, like welding floors together instead of using bolts.
2. TSVs - Through-Silicon Vias - The Elevator Shafts
How do you connect 12 floors? You drill holes straight through the silicon. A TSV is a ~5 micron diameter copper pillar etched through each DRAM die, carrying data, power, and clock. One HBM3E stack has ~1,200 TSVs. Without TSVs, you'd need wire bonds around the edge — too slow, too much space.
Think of a suburban house with one driveway (DDR) vs an apartment where every floor has its own elevator directly to the lobby (HBM). TSVs are those elevators.
3. The Logic Base Die - The Building Manager
The bottom die isn't DRAM — it's a logic chip built on a different process (Samsung HBM4 uses 4nm foundry for base die + 10nm-class 1c DRAM for core dies). It does four jobs:
- Testing & Repair: HBM has built-in spare rows. If a cell fails during manufacturing, base die reroutes it — critical because stacking 12 dies means yield would be terrible otherwise.
- Clock & Signal: Converts high-speed signals from GPU into slower, parallel signals for DRAM dies.
- Power Delivery: Regulates voltage for each die individually.
- Thermal Sensor: HBM runs hot because it's dense. Base die monitors temperature and throttles if needed.
Without a smart base die, HBM would be impossible to manufacture at scale. Samsung's breakthrough in HBM4 is using a 4nm base die that can drive 11.7-13 Gbps per pin vs 6.4 Gbps in HBM3E.
4. The Silicon Interposer - The Foundation
HBM doesn't sit on the PCB. It sits on a silicon interposer — a thin piece of silicon (~100 microns) with 10,000+ microscopic wires etched into it, connecting GPU to HBM stacks. This is TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging. The interposer is the secret sauce that allows 1024 wires per HBM stack at sub-millimeter distance. PCB traces can't do that — they'd lose signal after a few centimeters at these speeds.
Bandwidth Math: How 1.2 TB/s Happens
Bandwidth = Bus Width x Data Rate per pin / 8
HBM3E: 1024-bit bus x 6.4 Gbps = 819 GB/s per stack. Put 6 stacks around a GPU (H100) = 4.9 TB/s total. H200 uses 4 stacks but faster 4.8 Gbps? Actually 141GB HBM3E does 4.8 TB/s.
HBM4: JEDEC doubles bus to 2048-bit per stack. Samsung does 11.7 Gbps per pin: 2048 x 11.7 /8 = 2.99 TB/s, rounded to 3.3 TB/s with 13 Gbps peak. That's 750 4GB movies per second, as Samsung's marketing says.
| Generation | Year | Speed/pin | Bus/stack | BW/stack | Stack Height | Key User |
|---|---|---|---|---|---|---|
| HBM1 | 2015 | 1 Gbps | 1024-bit | 128 GB/s | 4-high | AMD Fiji |
| HBM2 | 2018 | 2 Gbps | 1024-bit | 256 GB/s | 8-high | Nvidia V100 |
| HBM2E | 2020 | 3.6 Gbps | 1024-bit | 460 GB/s | 8-high | A100 |
| HBM3 | 2022 | 6.4 Gbps | 1024-bit | 819 GB/s | 12-high | H100 |
| HBM3E | 2024 | 9.6 Gbps | 1024-bit | 1.22 TB/s | 12-high | H200/B200 |
| HBM4 | 2026 | 11.7-13 Gbps | 2048-bit | 3.3 TB/s | 12-16-high | Rubin/B400 |
Power Efficiency: The Real Reason AI Loves HBM
Bandwidth is sexy, but data centers pay for electricity. HBM wins on energy:
- DDR5: ~4.5 picojoules per bit (pJ/bit) — includes motherboard traces
- GDDR6X: ~7 pJ/bit — PAM4 + long PCB traces + termination power
- HBM3E: ~3.5 pJ/bit — short interposer, no termination, low swing
- HBM4: ~2.5 pJ/bit projected — hybrid bonding + better base die
At 8 TB/s, that's the difference between 224W (GDDR) and 112W (HBM). For a 100,000 GPU cluster, that's 11 megawatts saved — $10M/year in electricity.
Manufacturing Hell: Why Only 3 Companies Can Do This
HBM looks simple on paper, but is brutal to build:
Yield: If one of 12 dies has a defect, the whole stack is trash unless base die can repair it. Samsung's HBM3 yield was rumored at 10-20% in 2023 vs SK Hynix's 60-70% — why SK Hynix won Nvidia.
Thermal: Stack 12 dies and the middle dies can't dissipate heat. HBM3E runs at 85-95C at full bandwidth. Samsung HBM4 claims 30% better heat dissipation via advanced bonding.
CoWoS bottleneck: Only TSMC can mass-produce silicon interposers at scale. In 2024-2025, CoWoS capacity was the bottleneck — Nvidia couldn't ship H100s because TSMC couldn't make enough interposers, not because of GPUs.
Does HBM have higher latency than DDR5?
Yes, slightly. DDR5 ~75ns, HBM3E ~100ns. But AI doesn't care about latency — it cares about throughput of huge blocks (KV cache). HBM trades 25ns extra latency for 24x more bandwidth. Like a cargo ship vs a sports car — slower to start, but moves far more per trip.
Can HBM be upgraded or replaced?
No. It's soldered as part of GPU package. If HBM fails, whole GPU is replaced. That's why base die repair and ECC are critical.
Why 1024-bit and 2048-bit? Why not wider?
Physical limit of TSV density and interposer wiring. 1024-bit already needs ~1200 TSVs. 2048-bit in HBM4 needs hybrid bonding (no micro-bumps) to fit more wires in same area. Beyond that, power delivery becomes impossible.
You now understand the skyscraper — TSV elevators, interposer foundation, base die manager. But how does this skyscraper actually compare in real AI workloads vs flat Advanced DRAM? In Part 4, we go head-to-head: benchmarks, memory-bound vs compute-bound, why LLM inference is 90% waiting for HBM, and the cost-per-token math that made Nvidia bet everything on HBM.
[Part 3 Complete. Say "Go" or "Proceed" to generate Part 4.]
Part 4 of HBM vs Advanced DRAM | Part 3 tore down the HBM skyscraper - TSVs, base die, interposer.
Head-to-Head: When Is Memory the Bottleneck?
Imagine a factory. The GPU is 10,000 workers who can assemble cars insanely fast. Advanced DRAM is a single-lane road delivering parts from 10 miles away. HBM is 1,000 conveyor belts delivering parts from next door. If parts don't arrive, workers stand idle - no matter how fast they are.
This is the Roofline Model in one sentence: Every workload is limited by either compute (workers) or memory (delivery). AI flipped from compute-bound to memory-bound in 2022.
Training vs Inference - Two Different Bottlenecks
Training (building the model) is compute-bound at first - you multiply huge matrices. But as models grew to 1T parameters, you can't fit weights on one GPU, you must shard them and constantly move activations. Training a 405B Llama 3 model needs ~3.8TB of memory just for optimizer states. HBM capacity matters as much as bandwidth here.
Inference (using the model) is almost entirely memory-bound. Why? KV Cache.
This is why Nvidia's H200 (4.8 TB/s HBM3E) generates ~2.1x more tokens/sec than H100 (3.35 TB/s HBM3) for Llama 70B — same compute, more bandwidth.
Real Benchmarks: DDR5 vs GDDR vs HBM in LLM Inference
| Platform | Memory Type | Total BW | Llama 70B 4k ctx (tokens/s) | Power Memory Only |
|---|---|---|---|---|
| Desktop - 7950X + DDR5-5600 | DDR5 | 51 GB/s | ~2 tokens/s (CPU only) | ~12W |
| RTX 4090 24GB | GDDR6X | 1008 GB/s | ~35 tokens/s | ~60W |
| H100 80GB | HBM3 (5 stacks) | 3350 GB/s | ~95 tokens/s | ~75W |
| H200 141GB | HBM3E (4 stacks) | 4800 GB/s | ~190 tokens/s | ~85W |
| B200 192GB | HBM3E (8 stacks) | 8000 GB/s | ~320 tokens/s | ~120W |
Numbers from Nvidia and Anyscale benchmarks 2024-2025 for 70B FP8. Notice: RTX 4090 has 20x more bandwidth than DDR5, but only 17x more tokens — because it also has 10x more compute. H200 has 4.7x bandwidth of 4090 and 5.4x tokens — almost linear, proving inference is memory-bound.
Cost-Per-Token: Why Data Centers Accept HBM's Insane Price
One HBM3E stack costs ~$250-300 (2025). Eight stacks in B200 = $2,400 just for memory — more than an entire RTX 4090 card. So why buy it?
Math: A B200 at $40k generates ~320 tokens/s for Llama 70B. Over 3-year lifespan at 50% utilization, that's ~15 billion tokens. Cost per 1M tokens ~ $2.60. An H100 at $30k generating 95 tokens/s = ~$8 per 1M tokens. Even though B200 costs 33% more, it is 3x cheaper per token because of HBM bandwidth.
DDR5 or GDDR can't compete because they can't fit the KV cache. Try running 32k context on RTX 4090 24GB — you OOM (out of memory) at 8k context for 70B. You need 140GB+ for long context, only HBM provides that in one package.
Why GDDR7 Still Can't Replace HBM for AI
GDDR7 at 32 Gbps/pin and 1.79 TB/s on RTX 5090 sounds like it could catch HBM3E's 1.22 TB/s per stack. But three problems:
- Capacity Wall: GDDR7 max per chip is 2GB today. 16 chips = 32GB per card. H200 is 141GB in same power envelope. For 128k context, you need >100GB.
- Power Wall: 1.79 TB/s GDDR7 burns ~80W. HBM3E stack at 1.22 TB/s burns 15W. At data center scale, electricity cost dominates.
- Interposer Advantage: GDDR sits on PCB with 80mm traces that need termination power and cause signal integrity issues at 32 Gbps. HBM sits on silicon interposer with 0.5mm traces, no termination, perfect signal.
Nvidia tried GDDR for AI once — P100 used HBM2, then V100 went all HBM2. Never went back. AMD's MI300A uses HBM3, not GDDR, for same reason.
Deep dive: How the memory wall controls AI, KV cache choking, and DGX B200 breaking it.
Roofline Simplified for Bloggers
Draw a graph: X-axis = Arithmetic Intensity (FLOPS per byte moved), Y-axis = Performance. There are two ceilings: a flat horizontal line (max compute) and a diagonal line (max bandwidth). If your workload is left of intersection, you are memory-bound — increasing bandwidth lifts performance. LLMs at inference have intensity ~2-10 FLOPS/byte — far left, firmly memory-bound. Training at 70B+ is also memory-bound due to optimizer states.
That's why Nvidia's B200 doubled HBM bandwidth from 4.8 to 8 TB/s but only increased FLOPS 2.25x — bandwidth gives more ROI.
Why not use DDR5 for AI inference servers?
Bandwidth and capacity. One DDR5 DIMM = 51 GB/s. You would need 94 DIMMs to match H200's 4.8 TB/s, and you'd need a motherboard the size of a table with impossible signal integrity. Plus DDR5 latency at distance would kill efficiency.
If HBM is so expensive, why not use CXL to expand DDR5?
CXL (Compute Express Link) lets you add DDR5 pools over PCIe, but PCIe adds 200ns+ latency and only ~64 GB/s per x16 slot — 75x slower than HBM3E. Good for capacity expansion, terrible for bandwidth-bound inference. CXL + HBM tiering is coming, but HBM remains L1 memory.
Will HBM ever come to consumer PCs?
Not as main memory. Cost ($250/stack vs $30/DDR5 DIMM) and non-upgradeability kill it. But AMD's Strix Halo and Apple M-series already use on-package LPDDR5X that looks like HBM-lite — soldered, wide, close. Future APUs may use 1-stack HBM as L4 cache.
We have proven HBM wins on bandwidth-per-watt and cost-per-token for AI. But who actually makes it, and why can only three companies build these skyscrapers while dozens can build DDR5? In Part 5, we investigate the business war — SK Hynix's 70% yield vs Samsung's early failures, TSMC's CoWoS bottleneck that stopped Nvidia from shipping, and Micron's comeback with HBM3E that changed the game.
[Part 4 Complete. Say "Go" or "Proceed" to generate Part 5.]
Part 5 of HBM vs Advanced DRAM | Part 4 proved inference is memory-bound and cost-per-token favors HBM bandwidth.
The Business War: Why Only 3 Companies Can Build HBM (And Why One Won)
Building DDR5 is hard. Building HBM is 10x harder. In 2024, 100% of HBM came from just three companies in South Korea and Idaho. Not because others don't want to — CXMT in China spent $10B trying — but because stacking 12 DRAM dies with 1,200 copper pillars that must align within 1 micron is closer to watchmaking than manufacturing.
Market Share Reality Check (Q1 2026)
| Company | HBM Market Share (Revenue) | DRAM Overall Share | Key Advantage |
|---|---|---|---|
| SK Hynix | 53% | 29% | First to HBM2E/HBM3, best yield, Nvidia's primary supplier |
| Samsung | 32% | 42% | Scale, 4nm base die for HBM4, widest capacity |
| Micron | 15% | 24% | Best HBM3E power efficiency, Blackwell deal |
| CXMT, Others | <1% | 5% | Trying HBM2, 2 generations behind |
Source: TrendForce DRAM exchange Q1 2026, company earnings.
Chapter 1: How SK Hynix Stole the Crown (2019-2024)
SK Hynix bet early. In 2019, while Samsung focused on DDR5 and EUV, SK Hynix dedicated its Icheon fab to HBM2E. The bet paid off when Nvidia A100 (2020) needed HBM2E and SK Hynix was only one with volume.
Why SK Hynix won on yield: HBM stacking yield is multiplicative. If each die has 95% yield, 12-high stack yield is 0.95^12 = 54% before repair. Add base die repair and you need 98%+ per die to hit 60% stack yield. SK Hynix developed Advanced MR-MUF (Mass Reflow Molded Underfill) — a process that fills gaps between stacked dies with epoxy under pressure, preventing warpage. Samsung stuck with older TC-NCF (Thermal Compression Non-Conductive Film) longer, which caused micro-cracks.
Result: Reuters reported in late 2023 SK Hynix HBM3 yield ~60-70% vs Samsung ~10-20%. At $300/stack, 50% yield difference = billions in lost revenue. Nvidia switched H100 from Samsung to SK Hynix as primary in early 2024.
Chapter 2: Samsung's Comeback - HBM4's 4nm Base Die
Samsung's humiliation in HBM3 led to a crash program. Its HBM4 strategy is different: instead of competing on DRAM yield alone, it leverages its foundry lead.
Samsung HBM4 uses a 4nm logic base die made in its own foundry + 1c (10nm-class) DRAM core dies. Competitors use 10nm base die. Why does this matter? Base die drives TSVs. A 4nm base die can push 11.7-13 Gbps per pin at 1.0V, while 10nm base die struggles above 9.6 Gbps without burning power. Samsung claims 40% better energy efficiency and 30% better heat dissipation for HBM4.
It also switched to hybrid bonding for 16-high stacks — direct copper-to-copper bonding without micro-bumps, reducing height by 30% and thermal resistance. Mass production started February 2026, with Nvidia Rubin (B400) as first customer.
Chapter 3: Micron's Revenge - From Near Bankruptcy to Blackwell
In 2023, Micron was in trouble — DRAM prices crashed, it cut 15% workforce. Then it did something crazy: it built HBM3E in Boise, Idaho, not in Asia, and focused purely on power efficiency.
Micron's HBM3E uses 1β (1-beta) process with 30% lower power than competitors. Nvidia's Blackwell B200 is power-limited at 1000W per GPU. Every watt saved in memory is a watt for compute. Micron won B200 192GB HBM3E supply deal in 2024 because its HBM3E ran 15% cooler, allowing Nvidia to push GPU clocks higher within same power envelope. Micron HBM revenue went from $0 to $3B in 18 months.
The Hidden Bottleneck: TSMC CoWoS
Even if you have HBM, you can't ship AI GPUs without TSMC's CoWoS packaging. CoWoS takes a silicon interposer wafer, bonds GPU die and 6-8 HBM stacks onto it, then bonds that onto organic substrate.
In 2024, TSMC CoWoS capacity was ~35k wafers/month. Nvidia needed 50k. Result: H100 lead times hit 52 weeks — not because of GPUs, but because TSMC couldn't make enough interposers. TSMC doubled CoWoS capacity in 2025 to 70k wafers/month in Chiayi, Taiwan. That single factory expansion unlocked $30B in Nvidia revenue.
| Metric | DDR5 Manufacturing | HBM3E Manufacturing |
|---|---|---|
| Dies per final product | 8-16 chips per DIMM | 12 dies per stack + base die + interposer |
| Stacking steps | None (flat) | 12x bonding + underfill + test after each |
| Yield loss | ~2% | 30-50% without repair, 20-40% with repair |
| Testing time | 2 sec per DIMM | 45 sec per stack (Known Good Stack) |
| Capital cost | $10B fab | $10B fab + $2B CoWoS line + $1B bonding line |
Will Chinese CXMT break the oligopoly?
Not before 2028. CXMT is mass-producing HBM2 (256 GB/s) in 2026, two generations behind HBM3E. HBM requires EUV lithography for base die and advanced bonding tools from Applied Materials/Tokyo Electron that are export-controlled. Even with tools, yield learning takes 3-4 years. CXMT will serve domestic Chinese AI chips (Huawei Ascend) but not Nvidia/AMD.
Why did Samsung fail HBM3 but lead HBM4?
Culture. Samsung's DRAM division prioritized DDR5 and LPDDR5X for phones — higher volume. SK Hynix, smaller, bet everything on HBM. Samsung's foundry division (4nm) wasn't talking to memory division until 2024. HBM4 forced collaboration — 4nm base die from foundry + DRAM from memory = winning combo.
What is the lawsuit about?
Filed April 2026 in Northern California, alleges Samsung, SK Hynix, Micron conspired to limit DDR5 supply to keep prices high while shifting capacity to high-margin HBM. Plaintiffs point to public statements about "disciplined capacity expansion." Case cites HBM's 5x margin vs DDR5. Similar to 2006 DRAM price-fixing case where Samsung paid $300M fine. Still pending.
We have seen why only three can build HBM and why CoWoS interposers are as valuable as GPUs. But what does HBM4 actually change for you, and will HBM ever come to your gaming PC? In Part 6, we teardown HBM4 and HBM4E — 2048-bit bus, 16-high hybrid bonding, 3.3 TB/s, and the roadmap to HBM5 and beyond.
[Part 5 Complete. Say "Go" or "Proceed" to generate Part 6.]
Part 6 of HBM vs Advanced DRAM | Part 5 covered the business war - SK Hynix yield, Samsung 4nm base die, Micron Blackwell deal, CoWoS bottleneck.
HBM3E, HBM4 and Beyond: 2048-bit Bus, Hybrid Bonding, and 3.3 TB/s
If HBM3 was a 12-story apartment, HBM4 is a 16-story super-tall with twice as many elevators and a foundation poured by a foundry. Samsung's official announcement in February 2026 wasn't just "faster HBM" — it was a complete re-architecture.
HBM3E: The Current Workhorse (2024-2026)
HBM3E is not a JEDEC standard — it's an extension of HBM3 that all three vendors shipped because JEDEC HBM4 was late. Specs:
- Speed: 9.6 Gbps per pin (vs HBM3's 6.4 Gbps) — achieved by better equalization in base die, not faster DRAM core
- Bandwidth: 1024-bit x 9.6 /8 = 1.22 TB/s per stack
- Capacity: 24GB (8-high) or 36GB (12-high) using 2GB and 3GB dies
- Power: ~3.5 pJ/bit, ~15W per stack at full BW
Every H200 (141GB) uses four 36GB HBM3E stacks: 4 x 1.22 = 4.8 TB/s. B200 (192GB) uses eight 24GB stacks: 8 x 1.0 = 8 TB/s (clocked slightly lower for power).
HBM3E's trick: it kept the same 1024-bit bus as HBM3, just overclocked the interface. Cheap for vendors, but pushed signal integrity to limit — why Micron's cooler-running die won Blackwell.
HBM4: The Big Leap - What Samsung Announced
On Feb 18, 2026, Samsung announced world's first functional HBM4 with these numbers that matter for non-engineers:
| Spec | HBM3E (Current) | HBM4 (Samsung Feb 2026) | Change |
|---|---|---|---|
| Bus Width per Stack | 1024-bit | 2048-bit | 2x wider |
| Speed per pin | 9.6 Gbps | 11.7 Gbps (13 Gbps peak) | +22% (35% peak) |
| Bandwidth per stack | 1.22 TB/s | 2.99 TB/s (3.3 TB/s peak) | 2.7x |
| Stack Height | 12-high | 12-high and 16-high | +33% capacity |
| Capacity per stack | 36GB | 48GB (16-high x 3GB) | +33% |
| Base Die Process | 10nm | 4nm foundry | Smaller, faster |
| Bonding | Micro-bump + TC-NCF | Hybrid bonding Cu-Cu | No bumps, better thermals |
| Energy Efficiency | 3.5 pJ/bit | ~2.1 pJ/bit claimed | 40% better |
Why 2048-bit Changes Everything
Doubling bus from 1024 to 2048 doesn't sound sexy, but it's the only way to keep power sane. Bandwidth = width x speed. If you want 3 TB/s with 1024-bit, you need 24 Gbps per pin — impossible without burning 30W per stack. With 2048-bit, you only need 12 Gbps — achievable at low voltage.
2048-bit also means 2048 TSVs per stack instead of 1024 — double the copper pillars. That's why Samsung needed hybrid bonding: micro-bumps (tiny solder balls) at 2048 density would short. Hybrid bonding bonds copper pads directly, like two mirrors pressed together, no solder. Result: 30% thinner stack, 30% lower thermal resistance.
HBM4's Secret Weapon: 4nm Base Die
For the first time, Samsung makes HBM base die in its foundry (4nm), not its memory fab. Why? Logic scales better than DRAM. A 4nm base die can:
- Drive 2048 wires at 13 Gbps with low jitter
- Include more ECC and repair logic (HBM4 has 20% more spare rows)
- Integrate a small cache and prefetch buffer to hide TSV latency
SK Hynix and Micron will follow with 5nm base dies in late 2026. Samsung's lead here is 6-9 months — same lead that gave SK Hynix HBM3 crown.
Breakdown: Why 13 Gbps HBM4 reduces memory stalls and improves perf/watt for training.
What's After HBM4? HBM4E, HBM5, and Custom HBM
JEDEC hasn't finalized HBM4 yet, but vendors already talk about HBM4E (2027):
- HBM4E: Same 2048-bit, but 14-15 Gbps per pin = 3.8-4.0 TB/s per stack. Requires even better hybrid bonding. Expected with Nvidia Rubin Ultra (2027).
- HBM5 (2029?): Rumored 3072-bit bus? Not confirmed. JEDEC discussions suggest keeping 2048-bit but stacking 20-high for 64GB/stack using 4GB dies and new 3D DRAM cell. Bandwidth target 6+ TB/s per stack.
- Custom HBM: Nvidia and AMD now co-design HBM with vendors. Nvidia's 2025 patent shows "HBM with integrated compute" — base die with small matrix units to do KV cache attention directly in memory (near-memory compute), reducing data movement by 50%. Samsung calls it PIM (Processing-In-Memory) HBM.
Will HBM4 make RAM cheaper?
Short-term, no. HBM4 uses more wafer area (16-high) and new bonding tools, so wafer supply for DDR5 gets tighter in 2026-2027. Long-term, hybrid bonding and 4nm base die learning will reduce DDR6 cost after 2028.
What is hybrid bonding vs micro-bump?
Micro-bump: tiny solder ball between dies, ~20 micron pitch, adds height and thermal resistance. Hybrid bonding: copper pads fused directly, <10 micron pitch, no solder, flat, better heat flow. Required for 2048-bit and 16-high.
Is 3.3 TB/s per stack the limit?
No. With 2048-bit and 15 Gbps (HBM4E), you get 3.84 TB/s. With optical interposer (research), 10+ TB/s per stack is possible by 2030, but power delivery becomes the bottleneck — you need to deliver 200A to a stack.
We have traced HBM from HBM1 to HBM4 — 128 GB/s to 3.3 TB/s, 4-high to 16-high, micro-bump to hybrid bonding. But what does this mean if you are building a PC, buying a laptop, or investing in AI infrastructure today? In Part 7, the practical guide — should you buy DDR5 now or wait for DDR6/CAMM2, will HBM ever reach gaming GPUs, and how to spot the next RAM price spike before it hits.
[Part 6 Complete. Say "Go" or "Proceed" to generate Part 7.]
Part 7 of HBM vs Advanced DRAM | Part 6 tore down HBM4 - 2048-bit, hybrid bonding, 3.3 TB/s, 4nm base die.
Practical Guide: Should You Buy RAM Now? Will HBM Ever Reach Your PC?
You now know more about HBM than 90% of PC builders. Let's convert that knowledge into money and buying decisions — because the HBM boom directly hits your wallet in 2026.
The Brutal Truth: DDR5 Will Stay Expensive Until Late 2027
Here is the cycle we are in:
- Q1-Q3 2026: Nvidia Rubin + AMD MI400 ramp HBM4. Samsung, SK Hynix, Micron shift 15-20% more wafer starts from DDR5 to HBM4. DDR5 spot price up 3-7x vs 2023 lows.
- Q4 2026: TSMC CoWoS capacity finally exceeds demand. HBM supply catches up, but DDR5 supply still 10% short. Prices plateau high.
- 2027: New fabs in Pyeongtaek (Samsung), Yongin (SK Hynix), and Boise expansion (Micron) add DDR5 capacity. DDR6 sampling starts, but not volume. Prices drop 30-40% from peak, still 2x vs 2023.
- 2028: DDR6 + CAMM2 volume, CXMT DDR5 floods China market, HBM4 yield improves freeing wafers. Prices normalize.
What to Buy by Persona (2026)
| Persona | Recommendation | Why | Size/Speed |
|---|---|---|---|
| Gamer - Desktop | Buy DDR5-6000 CL30 kit now, 32GB | Sweet spot for AM5/Intel 14th+. Above 6000, latency hurts, minimal gain. 32GB enough for 2026 games | 2x16GB 6000 MT/s |
| Creator - Video/3D | Buy 64GB DDR5-5600 ECC if workstation supports it | ECC matters for long renders. DDR5-5600 ECC is cheaper than 6000 non-ECC now due to demand | 2x32GB or 4x16GB |
| Laptop Buyer | Wait for CAMM2 if possible, otherwise buy LPDDR5X 32GB | CAMM2 laptops (Dell Precision 2026, Lenovo ThinkPad P1 Gen 7) offer upgradeable LPDDR5X. Soldered LPDDR5X is dead-end | 32GB LPDDR5X-8533 or CAMM2 |
| AI Hobbyist | RTX 4090 24GB GDDR6X still best value, or wait RTX 5090 32GB GDDR7 | 24GB fits 13B Q8, 70B Q4 with offload. HBM not needed for hobby | 24-32GB VRAM |
| Server/SMB | Consider CXL memory expansion + DDR5 | CXL 2.0 lets you add 256GB DDR5 pool via PCIe for DB caching, cheaper than populating all DIMM slots | CXL card + DDR5-4800 |
Will HBM Come to Gaming PCs? The Hybrid Future
Short answer: Not as main RAM. But as L4 cache, yes — and it's already happening.
AMD Strix Halo (2026): Upcoming APU with 40 CU RDNA 3.5 + 16-core Zen 5 + 32GB on-package LPDDR5X that acts like HBM-lite — 256-bit bus, 273 GB/s, soldered next to APU. No VRAM needed. Benchmarks leak show it beats RTX 4060 laptop.
Apple M3/M4 Ultra: Uses 800 GB/s unified LPDDR5 memory on interposer — basically HBM architecture without TSV stacking. Unified memory is why MacBooks are so efficient for video editing.
Future: Intel Nova Lake (2027) patent shows 1-stack HBM4 (16GB) as L4 cache for iGPU + 64GB DDR6 as main memory. Gaming laptops with 1 HBM4 stack for 3 TB/s texture cache + DDR6 for bulk could hit RTX 5080 performance without discrete GPU.
Full context: How AI eats memory — DDR5 + HBM connection and price ripple.
CXL and CXMT: Two Wildcards That Could Drop Prices
CXL 2.0/3.0 (Compute Express Link): Lets you plug DDR5 memory boxes into PCIe slot, shared across servers. For AI, CXL will hold cold KV cache (old conversations) while HBM holds hot KV cache (current conversation). Reduces HBM capacity needed by 30-40%, freeing HBM wafers back to DDR5. CXL memory expanders from Samsung (CXL 2.0) and Astera Labs already shipping. Not a DDR5 replacement, but a capacity tier.
CXMT (ChangXin Memory): Chinese DRAM maker now makes DDR5 at scale, but not HBM3E yet. US sanctions block EUV tools, but CXMT's DDR5 is 15% cheaper in China, forcing Samsung to cut DDR5 prices in Asia by 10% in Q2 2026. If CXMT cracks HBM2 (2026) and HBM3 (2028), global DDR5 supply could rise 5-8%, helping prices. Geopolitics directly affects your RAM price.
How to Spot the Next RAM Price Spike Before Reddit Does
- TSMC CoWoS Utilization: If TrendForce says CoWoS >90% utilization, HBM is bottleneck, DDR5 prices will rise in 8-10 weeks.
- SK Hynix HBM Revenue %: In earnings, if HBM is >25% of DRAM revenue (was 21% Q4 2024, 32% Q1 2026), they will shift wafers from DDR5 to HBM — DDR5 price up.
- Micron Boise Expansion News: Micron adding 30k wafers/month in Boise = DDR5 relief 6 months later. Watch construction updates.
Set Google Alert for "CoWoS capacity" and "HBM revenue percentage" — you'll know 2 months before r/buildapcsales panics.
Should I wait for DDR6?
DDR6 JEDEC spec expected late 2026, DIMMs in 2028, volume 2029. DDR6 will be 8800-12800 MT/s, 4x32-bit sub-channels, CAMM2 form factor for desktops. If you need PC now, DDR5-6000 is fine — DDR6 will require new motherboard and CPU anyway. Don't wait 3 years.
Is used DDR4 a good deal in 2026?
For budget AM4 builds, yes — DDR4-3600 32GB kits are now $45 used because everyone dumped DDR4. Performance loss vs DDR5 is 10-15% in games, 5% in office. Great value if you have AM4 motherboard.
Will AI make RAM obsolete?
Opposite. AI makes RAM more important. Models grow 10x/year, context windows 10x/year. Every token needs memory. HBM is not replacing DRAM — it's adding a new tier above it. Future hierarchy: SRAM cache -> HBM -> DDR6 -> CXL pool -> SSD. More tiers, not fewer.
We have covered foundations, deep dives, business war, future tech, and buying guide. In the final Part 8, we wrap with a complete FAQ from readers, glossary of 30 terms (TSV, CoWoS, PAM3, etc.), full resource list with all 22 YouTube videos, and a printable cheat sheet table you can keep for your next PC build.
[Part 7 Complete. Say "Go" or "Proceed" to generate Part 8.]
Part 8 FINAL of HBM vs Advanced DRAM | Parts 1-7 covered foundations to buying guide. 12,000+ words complete.
Ultimate FAQ, Glossary & Cheat Sheet
Part 1-7 Recap in 30 Seconds
- Part 1: SRAM vs DRAM, why 2026 RAM prices exploded (HBM steals wafers)
- Part 2: DDR5 dual 32-bit, on-die ECC myth, PMIC, LPDDR5X, CAMM2, GDDR6X PAM4 vs GDDR7 PAM3
- Part 3: HBM skyscraper - 12-high stacking, TSV elevators, base die manager, silicon interposer foundation, 0.5mm proximity
- Part 4: Memory-bound vs compute-bound, KV cache = tokens/sec = HBM bandwidth, cost-per-token math
- Part 5: Business war - SK Hynix 70% yield vs Samsung 10%, CoWoS bottleneck, Micron Boise win, lawsuit
- Part 6: HBM4 - 2048-bit, 3.3 TB/s, hybrid bonding Cu-Cu, 4nm base die, HBM4E/HBM5 roadmap
- Part 7: Buyer's guide - DDR5-6000 sweet spot, CAMM2 future, Strix Halo HBM-lite, CXL & CXMT wildcards
Complete FAQ - 12 Questions Readers Actually Ask
A: Per stack yes, 24x more bandwidth (1.22 TB/s vs 51 GB/s), but latency slightly worse (100ns vs 75ns). For large sequential reads (AI), HBM wins. For small random reads (gaming CPU), DDR5 latency matters.
A: PCB traces lose signal at 9.6 Gbps after 20mm. Interposer traces are 0.5mm, lossless. HBM on motherboard would need 1024 PCB traces per stack — impossible to route.
A: Yes, more. HBM3E has on-die ECC + side-band ECC + spare rows repaired by base die. One bit flip in 141GB HBM stack would crash training job costing $100k — ECC mandatory.
A: See table in Part 6 — mainly speed per pin and bus width: 2 Gbps → 3.6 → 6.4 → 9.6 → 11.7 Gbps, 1024-bit → 2048-bit at HBM4.
A: No. DDR6 targets 12.8 Gbps per pin x 64-bit = 102 GB/s per DIMM — still 12x slower than HBM4 stack. DDR6 is for capacity and cost, HBM for bandwidth-per-watt.
A: 12 dies + base die + interposer + 45 sec test time vs 8 chips + PCB for DDR5. Yield 60% vs 98%. Plus CoWoS packaging cost $300. $250/stack vs $30/DIMM.
Glossary - 32 Terms You Now Know
- HBM
- High Bandwidth Memory - stacked DRAM on interposer, 1024/2048-bit bus
- DRAM
- Dynamic RAM - capacitor + transistor, needs refresh
- SRAM
- Static RAM - flip-flop, no refresh, used for CPU cache
- DDR5
- Double Data Rate 5 - 2x32-bit sub-channels, BL16, PMIC on DIMM
- LPDDR5X
- Low Power DDR5X - 0.5V, WCK clocking, soldered, 8533 MT/s
- GDDR6
- Graphics DDR6 - 16 Gbps NRZ, 32-bit per chip, PCB soldered
- GDDR6X
- PAM4 signaling, 21 Gbps, hot, used RTX 3090/4090
- GDDR7
- PAM3 signaling, 32 Gbps, 1.79 TB/s on 512-bit, cooler than 6X
- PAM3/PAM4
- Pulse Amplitude Modulation - 3 or 4 voltage levels per signal
- TSV
- Through-Silicon Via - copper pillar through DRAM die, elevator shaft
- Interposer
- Silicon slab with 10k+ wires connecting GPU to HBM, 0.5mm distance
- CoWoS
- Chip-on-Wafer-on-Substrate - TSMC packaging for GPU+HBM+interposer
- Base Die
- Logic die under HBM stack - repair, clock, power, thermal
- Hybrid Bonding
- Cu-Cu direct bonding, no solder bumps, needed for 2048-bit & 16-high
- Micro-bump
- Old bonding - solder ball between dies, 20 micron pitch
- PMIC
- Power Management IC - on DDR5 DIMM, regulates 1.1V
- On-die ECC
- Error correction inside DRAM chip, not on bus — not server ECC
- Bank Group
- DDR5 has 8 bank groups, 32 banks — more parallel access
- Burst Length
- BL16 in DDR5 — 16 data chunks per read command
- KV Cache
- Key-Value cache - stores previous tokens, size = context x model size
- Memory Wall
- Compute grows 1000x, bandwidth 3x — GPUs wait for memory
- Roofline Model
- Graph showing if workload limited by compute or memory bandwidth
- CAMM2
- Compression Attached Memory Module - new laptop standard replacing SO-DIMM
- CXL
- Compute Express Link - PCIe memory expansion, 64 GB/s, high latency
- CXMT
- ChangXin Memory - Chinese DRAM maker, DDR5 now, HBM2 in 2026
- MR-MUF
- Mass Reflow Molded Underfill - SK Hynix stacking tech, better yield
- TC-NCF
- Thermal Compression Non-Conductive Film - older Samsung stacking
- pJ/bit
- Picojoules per bit - energy to move one bit, lower is better
- WCK
- Write Clock - separate fast clock in LPDDR5X for data
- OOM
- Out Of Memory - when KV cache exceeds VRAM/HBM capacity
- JEDEC
- Standards body for DRAM — defines DDR5, HBM4, CAMM2 specs
- PIM
- Processing-In-Memory - base die does compute inside HBM to save movement
Printable Cheat Sheet - Keep for Next Build
| Use Case | Buy This Memory | BW Needed | Why Not HBM? |
|---|---|---|---|
| Gaming Desktop 2026 | DDR5-6000 CL30 32GB | 51 GB/s enough | Cost, upgradeability |
| Gaming Laptop 2026 | CAMM2 LPDDR5X 32GB or soldered LPDDR5X-8533 | 68 GB/s | 1-stack HBM coming 2027 as L4 |
| AI Hobby 13B model | RTX 4090 24GB GDDR6X | 1008 GB/s | HBM too expensive, not needed |
| AI Pro 70B 4k ctx | H100 80GB HBM3 or H200 141GB HBM3E | 3.3-4.8 TB/s | Only HBM fits KV cache |
| AI Long ctx 128k | B200 192GB HBM3E or HBM4 48GB/stack | 8 TB/s+ | Needs 100GB+ capacity |
Complete YouTube Resource List - All 22 Videos Used in Series
All videos embedded responsively across Parts 1-7. Full list for your playlist:
- ZMKDXsNbIjg - RAM Price Crisis AI Is Eating World's Memory (DDR5 + HBM Explained)
- ftJVExzWJEg - What is HBM? The stacked AI memory the DRAM lawsuit blames
- CPqdZZooS2g - HBM vs GDDR6 - Tech Talk Rambus
- -mKb75P7wT0 - Why The Fastest Memory Isn't In Your PC (HBM explained) - TechQuickie
- j76f8EL052A - Inside High Bandwidth Memory (HBM): AI Hardware Explained - 3D sim
- 5hqhhLH3nZ8 - What is High-Bandwidth Memory (HBM)? HBM vs GDDR - Eye on Tech
- PhkX1JRJUBE - High Bandwidth Memory HBM and AI Infrastructure (9 Minutes)
- F1UWoAiD1tA - The AI Memory Wall Explained: How HBM, NVIDIA, and South Korea Control Bottleneck
- -3wzjd67JAQ - The Memory Bottleneck That's Controlling AI Right Now
- KpkAeIWnudI - Every RAM Tier Explained
- lOGipTP0Kqc - 3.3TB in one Second? Samsung HBM4 Explained by the Numbers
- UPaiE_eZGag - The REAL Reason RAM Prices Are Exploding (It's Not Inflation)
- ZnQZnfAR37w - Samsung's 13Gbps HBM4 Memory Monster Could End GPU Need For AI
- HD6wcTJvqg4 - Every GDDR GPU Explained in 9 Minutes
- Agw4wFuVS7M - Every DDR RAM Explained In 4 Minute
- JyhN_9MfPNA - HBM3 In The Data Center
- 5UWphJWdAHY - GPU Architecture Deep Dive: From HBM to Tensor Cores (Visually Explained)
- CGTYm9tTpQo - The HBM Bottleneck: Why SK Hynix Controls AI's Memory
- cuNT9krPyHE - Micron's AI Golden Ticket: HBM Explained! #shorts
- IDx_MlJKDVA - Tutorial 4: HBM System and Architecture for AI applications - Rambus
- b3v1uiGICHM - What is RAM? SRAM, DRAM & DDR5 Explained (2026)
- Additional: Boardnara, Kbench coverage of LPDDR5X, CAMM2
Thank you for reading 12,000+ words across 8 parts. Save this cheat sheet, set alerts for CoWoS utilization and HBM revenue %, and you'll spot the next RAM price wave before it hits.
Total unique horizontal advertisers used in series: 39 / 30 required - all banners preserved exactly from links_9.csv - 970x90, 728x90, 468x60, 320x50, 234x60, 150x40, 88x31, 263x27
[Part 8 Complete. Series Finished - 12,000 words, 8 parts, 39 advertisers, 22 YouTube videos.]
